2024年10月22日发(作者：锺离冬萱)
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
D
D
D
D
D
2-V to 5.5-V V
CC
Operation
Unbuffered Outputs
Max t
pd
of 6.5 ns at 5 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25°C
D
Support Mixed-Mode Voltage Operation on
D
D
All Ports
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
FK PACKAGE
(TOP VIEW)
V
C
C
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
6A
6Y
5A
5Y
4A
4Y
1
A
114
13
6A
12
6Y
11
5A
10
5Y
9
4A
1
Y
1
A
N
C
V
C
C
6
A
2A
NC
2Y
NC
3A
4
5
6
7
8
3212019
18
17
16
15
14
910111213
J OR W PACKAGE
D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1Y
2A
2Y
3A
3Y
2
3
4
5
6
78
6Y
NC
5A
NC
5Y
G
N
D
NC − No internal connection
description/ordering information
These hex inverters are designed for 2-V to 5.5-V V
CC
operation.
The ’LVU04A devices contain six independent inverters with unbuffered outputs. These devices perform the
Boolean function Y = A.
ORDERING INFORMATION
T
A
PACKAGE
†
QFN − RGY
SOIC − D
SOP − NS
−40°C to 85°C
SSOP − DB
TSSOP − PW
TVSOP − DGV
CDIP − J
−55
°
C to 125
°
CCFP − W
LCCC − FK
Reel of 1000
Tube of 50
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
Tube of 150
Tube of 85
ORDERABLE
PART NUMBER
SN74LVU04ARGYR
SN74LVU04AD
SN74LVU04ADR
SN74LVU04ANSR
SN74LVU04ADBR
SN74LVU04APW
SN74LVU04APWR
SN74LVU04APWT
SN74LVU04ADGVR
SNJ54LVU04AJ
SNJ54LVU04AW
SNJ54LVU04AFK
LU04A
SNJ54LVU04AJ
SNJ54LVU04AW
SNJ54LVU04AFK
LU04A
TOP-SIDE
MARKING
LVU04A
LVU04A
LVU04A
LU04A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at /sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
•
3
Y
G
N
D
N
C
4
Y
4
A
4
Y
1
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
FUNCTION TABLE
(each inverter)
INPUT
A
H
L
OUTPUT
Y
L
H
logic diagram, each inverter (positive logic)
AY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θ
JA
(see Note 3):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 3):DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 3):DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 3):NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 3):PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 4):RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
stg
−65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: input and output voltage ratings may be exceeded if the input and output current ratings are observed.
value is limited to 5.5 V maximum.
package thermal impedance is calculated in accordance with JESD 51-7.
package thermal impedance is calculated in accordance with JESD 51-5.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
recommended operating conditions (see Note 5)
SN54LVU04A
MIN
V
CC
Supply voltage
V
CC
= 2 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 2 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
0
0
V
CC
= 2 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 2 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
2
1.7
V
CC
×0.8
V
CC
×0.8
V
CC
×0.8
0.3
V
CC
×0.2
V
CC
×0.2
V
CC
×0.2
5.5
V
CC
−50
−2
−6
−12
50
2
6
12
0
0
MAX
5.5
SN74LVU04A
MIN
2
1.7
V
CC
×0.8
V
CC
×0.8
V
CC
×0.8
0.3
V
CC
×0.2
V
CC
×0.2
V
CC
×0.2
5.5
V
CC
−50
−2
−6
−12
50
2
6
12
mA
µA
mA
V
V
MAX
5.5
UNIT
V
V
IH
High-level input voltage
V
IL
Low-level input voltage
V
I
V
O
Input voltage
Output voltage
V
V
µA
I
OH
High-level output current
I
OL
Low-level output current
T
A
Operating free-air temperature−55125−4085°C
NOTE 5:All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETERTEST CONDITIONS
I
OH
= −50 µA
I
OH
= −2 mA
I
OH
= −6 mA
I
OH
= −12 mA
I
OL
= 50 µA
I
OL
= 2 mA
I
OL
= 6 mA
I
OL
= 12 mA
V
I
= 5.5 V or GND
V
I
= V
CC
or GND,
V
I
= V
CC
or GND
I
O
= 0
V
CC
2 V to 5.5 V
2.3 V
3 V
4.5 V
2 V to 5.5 V
2.3 V
3 V
4.5 V
0 V to 5.5 V
5.5 V
3.3 V4
SN54LVU04A
MIN
V
CC
−0.1
2
2.48
3.8
0.1
0.4
0.44
0.55
±1
20
4
TYPMAX
SN74LVU04A
MIN
V
CC
−0.1
2
2.48
3.8
0.1
0.4
0.44
0.55
±1
20
µA
µA
pF
V
TYPMAX
UNIT
V
OH
V
V
OL
I
I
I
CC
C
i
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
3
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
LOAD
CAPACITANCE
C
L
= 15 pF
C
L
= 50 pF
T
A
= 25°C
MINTYPMAX
3.2*
6.6
10.9*
13.4
SN54LVU04A
MIN
1*
1
MAX
14*
16
SN74LVU04A
MIN
1
1
MAX
14
16
UNIT
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
LOAD
CAPACITANCE
C
L
= 15 pF
C
L
= 50 pF
T
A
= 25°C
MINTYPMAX
2.5*
4.7
8.9*
11.4
SN54LVU04A
MIN
1*
1
MAX
10.5*
13
SN74LVU04A
MIN
1
1
MAX
10.5
13
UNIT
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
LOAD
CAPACITANCE
C
L
= 15 pF
C
L
= 50 pF
T
A
= 25°C
MINTYPMAX
2.2*
3.9
5.5*
7
SN54LVU04A
MIN
1*
1
MAX
6.5*
8
SN74LVU04A
MIN
1
1
MAX
6.5
8
UNIT
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
CC
= 3.3 V, C
L
= 50 pF, T
A
= 25°C (see Note 6
)
PARAMETER
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
Quiet output, maximum dynamic V
OL
Quiet output, minimum dynamic V
OL
Quiet output, minimum dynamic V
OH
High-level dynamic input voltage2.31
0.99
SN74LVU04A
MINTYP
0.5
−0.1
3
MAX
0.8
−0.8
UNIT
V
V
V
V
VV
IL(D)
Low-level dynamic input voltage
NOTE 6:Characteristics are for surface-mount packages only.
operating characteristics, T
A
= 25°C
PARAMETER
C
pd
Power dissipation capacitance
TEST CONDITIONS
C
L
= 50 pF,f = 10 MHz
V
CC
3.3 V
5 V
TYP
5.6
6.7
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
R
L
= 1 kΩ
S1
V
CC
Open
GND
From Output
Under Test
C
L
(see Note A)
Test
Point
From Output
Under Test
C
L
(see Note A)
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open Drain
S1
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
0 V
V
CC
t
su
Data Input
0 V
50% V
CC
t
h
V
CC
50% V
CC
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
CC
Output
Control
t
PZL
Output
Waveform 1
S1 at V
CC
(see Note B)
t
PZH
Output
Waveform 2
S1 at GND
(see Note B)
50% V
CC
50% V
CC
V
CC
50% V
CC
50% V
CC
t
PLZ
≈V
CC
V
OL
+ 0.3 V
V
OL
t
PHZ
V
OH
− 0.3 V
V
OH
≈0 V
0 V
Timing Input
t
w
50% V
CC
Input
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
50% V
CC
50% V
CC
t
PHL
0 V
50% V
CC
V
OH
50% V
CC
V
OL
t
PLH
50% V
CC
V
OH
50% V
CC
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES:A.C
L
includes probe and jig capacitance.
rm 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, Z
O
= 50 Ω, t
r
≤3 ns, t
f
≤ 3 ns.
outputs are measured one at a time, with one input transition per measurement.
E.t
PLZ
and t
PHZ
are the same as t
dis
.
F.t
PZL
and t
PZH
are the same as t
en
.
G.t
PHL
and t
PLH
are the same as t
pd
.
parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
5
PACKAGE OPTION ADDENDUM
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
SN74LVU04AD
SN74LVU04ADBR
SN74LVU04ADG4
SN74LVU04ADR
SN74LVU04ANSR
SN74LVU04APW
SN74LVU04APWR
SN74LVU04APWRG4
SN74LVU04APWT
SN74LVU04APWTE4
(1)
Status
(1)
Package TypePackagePinsPackage
DrawingQty
SOIC
SSOP
SOIC
SOIC
SO
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
D
DB
D
D
NS
PW
PW
PW
PW
PW
14
14
14
14
14
14
14
14
14
14
50
2000
50
2500
2000
90
2000
2000
250
250
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
(4/5)
Samples
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
LVU04A
LU04A
LVU04A
LVU04A
LVU04A
LU04A
LU04A
LU04A
LU04A
LU04A
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
24-Aug-2018
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVU04A :
•
Automotive: SN74LVU04A-Q1
NOTE: Qualified Version Definitions:
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGEMATERIALSINFORMATION
20-Dec-2018
TAPEANDREELINFORMATION
*Alldimensionsarenominal
DevicePackagePackagePins
TypeDrawing
SOIC
SO
TSSOP
TSSOP
D
NS
PW
PW
14
14
14
14
SPQReelReelA0
DiameterWidth(mm)
(mm)W1(mm)
330.0
330.0
330.0
330.0
16.4
16.4
12.4
12.4
6.5
8.2
6.9
6.9
B0
(mm)
9.0
10.5
5.6
5.6
K0
(mm)
2.1
2.5
1.6
1.6
P1
(mm)
8.0
12.0
8.0
8.0
WPin1
(mm)Quadrant
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
SN74LVU04ADR
SN74LVU04ANSR
SN74LVU04APWR
SN74LVU04APWT
2500
2000
2000
250
PackMaterials-Page1
PACKAGEMATERIALSINFORMATION
20-Dec-2018
*Alldimensionsarenominal
Device
SN74LVU04ADR
SN74LVU04ANSR
SN74LVU04APWR
SN74LVU04APWT
PackageType
SOIC
SO
TSSOP
TSSOP
PackageDrawing
D
NS
PW
PW
Pins
14
14
14
14
SPQ
2500
2000
2000
250
Length(mm)
367.0
367.0
367.0
367.0
Width(mm)
367.0
367.0
367.0
367.0
Height(mm)
38.0
38.0
35.0
35.0
PackMaterials-Page2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN
0,65
28
0,38
0,22
15
0,15
M
PLASTIC SMALL-OUTLINE
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
A
14
0°–ā8°
0,25
0,95
0,55
Seating Plane
2,00 MAX
0,05 MIN
0,10
PINS **
DIM
A MAX
14
6,50
16
6,50
20
7,50
24
8,50
28
10,50
30
10,50
38
12,90
A MIN
5,905,906,907,909,90
9,9012,30
4040065/E 12/01
NOTES:A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
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PARTYINTELLECTUALPROPERTYRIGHTS.
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MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265
Copyright©2018,TexasInstrumentsIncorporated
2024年10月22日发(作者：锺离冬萱)
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
D
D
D
D
D
2-V to 5.5-V V
CC
Operation
Unbuffered Outputs
Max t
pd
of 6.5 ns at 5 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25°C
D
Support Mixed-Mode Voltage Operation on
D
D
All Ports
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
FK PACKAGE
(TOP VIEW)
V
C
C
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
6A
6Y
5A
5Y
4A
4Y
1
A
114
13
6A
12
6Y
11
5A
10
5Y
9
4A
1
Y
1
A
N
C
V
C
C
6
A
2A
NC
2Y
NC
3A
4
5
6
7
8
3212019
18
17
16
15
14
910111213
J OR W PACKAGE
D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1Y
2A
2Y
3A
3Y
2
3
4
5
6
78
6Y
NC
5A
NC
5Y
G
N
D
NC − No internal connection
description/ordering information
These hex inverters are designed for 2-V to 5.5-V V
CC
operation.
The ’LVU04A devices contain six independent inverters with unbuffered outputs. These devices perform the
Boolean function Y = A.
ORDERING INFORMATION
T
A
PACKAGE
†
QFN − RGY
SOIC − D
SOP − NS
−40°C to 85°C
SSOP − DB
TSSOP − PW
TVSOP − DGV
CDIP − J
−55
°
C to 125
°
CCFP − W
LCCC − FK
Reel of 1000
Tube of 50
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
Tube of 150
Tube of 85
ORDERABLE
PART NUMBER
SN74LVU04ARGYR
SN74LVU04AD
SN74LVU04ADR
SN74LVU04ANSR
SN74LVU04ADBR
SN74LVU04APW
SN74LVU04APWR
SN74LVU04APWT
SN74LVU04ADGVR
SNJ54LVU04AJ
SNJ54LVU04AW
SNJ54LVU04AFK
LU04A
SNJ54LVU04AJ
SNJ54LVU04AW
SNJ54LVU04AFK
LU04A
TOP-SIDE
MARKING
LVU04A
LVU04A
LVU04A
LU04A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at /sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
•
3
Y
G
N
D
N
C
4
Y
4
A
4
Y
1
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
FUNCTION TABLE
(each inverter)
INPUT
A
H
L
OUTPUT
Y
L
H
logic diagram, each inverter (positive logic)
AY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θ
JA
(see Note 3):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 3):DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 3):DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 3):NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 3):PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 4):RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
stg
−65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: input and output voltage ratings may be exceeded if the input and output current ratings are observed.
value is limited to 5.5 V maximum.
package thermal impedance is calculated in accordance with JESD 51-7.
package thermal impedance is calculated in accordance with JESD 51-5.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
recommended operating conditions (see Note 5)
SN54LVU04A
MIN
V
CC
Supply voltage
V
CC
= 2 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 2 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
0
0
V
CC
= 2 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 2 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
2
1.7
V
CC
×0.8
V
CC
×0.8
V
CC
×0.8
0.3
V
CC
×0.2
V
CC
×0.2
V
CC
×0.2
5.5
V
CC
−50
−2
−6
−12
50
2
6
12
0
0
MAX
5.5
SN74LVU04A
MIN
2
1.7
V
CC
×0.8
V
CC
×0.8
V
CC
×0.8
0.3
V
CC
×0.2
V
CC
×0.2
V
CC
×0.2
5.5
V
CC
−50
−2
−6
−12
50
2
6
12
mA
µA
mA
V
V
MAX
5.5
UNIT
V
V
IH
High-level input voltage
V
IL
Low-level input voltage
V
I
V
O
Input voltage
Output voltage
V
V
µA
I
OH
High-level output current
I
OL
Low-level output current
T
A
Operating free-air temperature−55125−4085°C
NOTE 5:All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETERTEST CONDITIONS
I
OH
= −50 µA
I
OH
= −2 mA
I
OH
= −6 mA
I
OH
= −12 mA
I
OL
= 50 µA
I
OL
= 2 mA
I
OL
= 6 mA
I
OL
= 12 mA
V
I
= 5.5 V or GND
V
I
= V
CC
or GND,
V
I
= V
CC
or GND
I
O
= 0
V
CC
2 V to 5.5 V
2.3 V
3 V
4.5 V
2 V to 5.5 V
2.3 V
3 V
4.5 V
0 V to 5.5 V
5.5 V
3.3 V4
SN54LVU04A
MIN
V
CC
−0.1
2
2.48
3.8
0.1
0.4
0.44
0.55
±1
20
4
TYPMAX
SN74LVU04A
MIN
V
CC
−0.1
2
2.48
3.8
0.1
0.4
0.44
0.55
±1
20
µA
µA
pF
V
TYPMAX
UNIT
V
OH
V
V
OL
I
I
I
CC
C
i
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
3
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
LOAD
CAPACITANCE
C
L
= 15 pF
C
L
= 50 pF
T
A
= 25°C
MINTYPMAX
3.2*
6.6
10.9*
13.4
SN54LVU04A
MIN
1*
1
MAX
14*
16
SN74LVU04A
MIN
1
1
MAX
14
16
UNIT
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
LOAD
CAPACITANCE
C
L
= 15 pF
C
L
= 50 pF
T
A
= 25°C
MINTYPMAX
2.5*
4.7
8.9*
11.4
SN54LVU04A
MIN
1*
1
MAX
10.5*
13
SN74LVU04A
MIN
1
1
MAX
10.5
13
UNIT
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
LOAD
CAPACITANCE
C
L
= 15 pF
C
L
= 50 pF
T
A
= 25°C
MINTYPMAX
2.2*
3.9
5.5*
7
SN54LVU04A
MIN
1*
1
MAX
6.5*
8
SN74LVU04A
MIN
1
1
MAX
6.5
8
UNIT
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
CC
= 3.3 V, C
L
= 50 pF, T
A
= 25°C (see Note 6
)
PARAMETER
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
Quiet output, maximum dynamic V
OL
Quiet output, minimum dynamic V
OL
Quiet output, minimum dynamic V
OH
High-level dynamic input voltage2.31
0.99
SN74LVU04A
MINTYP
0.5
−0.1
3
MAX
0.8
−0.8
UNIT
V
V
V
V
VV
IL(D)
Low-level dynamic input voltage
NOTE 6:Characteristics are for surface-mount packages only.
operating characteristics, T
A
= 25°C
PARAMETER
C
pd
Power dissipation capacitance
TEST CONDITIONS
C
L
= 50 pF,f = 10 MHz
V
CC
3.3 V
5 V
TYP
5.6
6.7
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
SN54LVU04A, SN74LVU04A
HEX INVERTERS
SCES130L − MARCH 1998 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
R
L
= 1 kΩ
S1
V
CC
Open
GND
From Output
Under Test
C
L
(see Note A)
Test
Point
From Output
Under Test
C
L
(see Note A)
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open Drain
S1
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
0 V
V
CC
t
su
Data Input
0 V
50% V
CC
t
h
V
CC
50% V
CC
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
CC
Output
Control
t
PZL
Output
Waveform 1
S1 at V
CC
(see Note B)
t
PZH
Output
Waveform 2
S1 at GND
(see Note B)
50% V
CC
50% V
CC
V
CC
50% V
CC
50% V
CC
t
PLZ
≈V
CC
V
OL
+ 0.3 V
V
OL
t
PHZ
V
OH
− 0.3 V
V
OH
≈0 V
0 V
Timing Input
t
w
50% V
CC
Input
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
50% V
CC
50% V
CC
t
PHL
0 V
50% V
CC
V
OH
50% V
CC
V
OL
t
PLH
50% V
CC
V
OH
50% V
CC
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES:A.C
L
includes probe and jig capacitance.
rm 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, Z
O
= 50 Ω, t
r
≤3 ns, t
f
≤ 3 ns.
outputs are measured one at a time, with one input transition per measurement.
E.t
PLZ
and t
PHZ
are the same as t
dis
.
F.t
PZL
and t
PZH
are the same as t
en
.
G.t
PHL
and t
PLH
are the same as t
pd
.
parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
5
PACKAGE OPTION ADDENDUM
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
SN74LVU04AD
SN74LVU04ADBR
SN74LVU04ADG4
SN74LVU04ADR
SN74LVU04ANSR
SN74LVU04APW
SN74LVU04APWR
SN74LVU04APWRG4
SN74LVU04APWT
SN74LVU04APWTE4
(1)
Status
(1)
Package TypePackagePinsPackage
DrawingQty
SOIC
SSOP
SOIC
SOIC
SO
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
D
DB
D
D
NS
PW
PW
PW
PW
PW
14
14
14
14
14
14
14
14
14
14
50
2000
50
2500
2000
90
2000
2000
250
250
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
(4/5)
Samples
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
LVU04A
LU04A
LVU04A
LVU04A
LVU04A
LU04A
LU04A
LU04A
LU04A
LU04A
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
24-Aug-2018
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVU04A :
•
Automotive: SN74LVU04A-Q1
NOTE: Qualified Version Definitions:
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGEMATERIALSINFORMATION
20-Dec-2018
TAPEANDREELINFORMATION
*Alldimensionsarenominal
DevicePackagePackagePins
TypeDrawing
SOIC
SO
TSSOP
TSSOP
D
NS
PW
PW
14
14
14
14
SPQReelReelA0
DiameterWidth(mm)
(mm)W1(mm)
330.0
330.0
330.0
330.0
16.4
16.4
12.4
12.4
6.5
8.2
6.9
6.9
B0
(mm)
9.0
10.5
5.6
5.6
K0
(mm)
2.1
2.5
1.6
1.6
P1
(mm)
8.0
12.0
8.0
8.0
WPin1
(mm)Quadrant
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
SN74LVU04ADR
SN74LVU04ANSR
SN74LVU04APWR
SN74LVU04APWT
2500
2000
2000
250
PackMaterials-Page1
PACKAGEMATERIALSINFORMATION
20-Dec-2018
*Alldimensionsarenominal
Device
SN74LVU04ADR
SN74LVU04ANSR
SN74LVU04APWR
SN74LVU04APWT
PackageType
SOIC
SO
TSSOP
TSSOP
PackageDrawing
D
NS
PW
PW
Pins
14
14
14
14
SPQ
2500
2000
2000
250
Length(mm)
367.0
367.0
367.0
367.0
Width(mm)
367.0
367.0
367.0
367.0
Height(mm)
38.0
38.0
35.0
35.0
PackMaterials-Page2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN
0,65
28
0,38
0,22
15
0,15
M
PLASTIC SMALL-OUTLINE
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
A
14
0°–ā8°
0,25
0,95
0,55
Seating Plane
2,00 MAX
0,05 MIN
0,10
PINS **
DIM
A MAX
14
6,50
16
6,50
20
7,50
24
8,50
28
10,50
30
10,50
38
12,90
A MIN
5,905,906,907,909,90
9,9012,30
4040065/E 12/01
NOTES:A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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•
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