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2024年5月28日发(作者：漫滢渟)

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DS91M040 125 MHz Quad M-LVDS Transceiver

May 13, 2008

DS91M040

125 MHz Quad M-LVDS Transceiver

General Description

The DS91M040 is a quad M-LVDS transceiver designed for

driving / receiving clock or data signals to / from up to four

multipoint networks.

M-LVDS (Multipoint LVDS) is a new family of bus interface

devices based on LVDS technology specifically designed for

multipoint and multidrop cable and backplane applications. It

differs from standard LVDS in providing increased drive cur-

rent to handle double terminations that are required in multi-

point applications. Controlled transition times minimize re-

flections that are common in multipoint configurations due to

unterminated stubs. M-LVDS devices also have a very large

input common mode voltage range for additional noise margin

in heavily loaded and noisy backplane environments.

A single DS91M040 channel is a half-duplex transceiver that

accepts LVTTL/LVCMOS signals at the driver inputs and con-

verts them to differential M-LVDS signal levels. The receiver

inputs accept low voltage differential signals (LVDS, BLVDS,

M-LVDS, LVPECL and CML) and convert them to 3V LVC-

MOS signals. The DS91M040 supports both M-LVDS type 1

and type 2 receiver inputs.

Features

■

DC - 125 MHz / 250 Mbps low jitter, low skew, low power

■

operation

Wide Input Common Mode Voltage Range allows up to

±2V of GND noise

Conforms to TIA/EIA-899 M-LVDS Standard

Pin selectable M-LVDS receiver type (1 or 2)

Controlled transition times (2.0 ns typ) minimize reflections

8 kV ESD on M-LVDS I/O pins protects adjoining

components

Flow-through pinout simplifies PCB layout

Small 5 mm x 5 mm LLP-32 space saving package

Applications

■

Multidrop / Multipoint clock and data distribution

■

High-Speed, Low Power, Short-Reach alternative to TIA/

EIA-485/422

■

Clock distribution in AdvancedTCA (ATCA) and

MicroTCA (μTCA) backplanes

Typical Application

30042202

元器件交易网

Ordering Information

Order Number

DS91M040TSQ

Receiver Input

Type 1 or 2

Function

Quad M-LVDS Transciever

Package Type

LLP-32

Connection Diagram

30042201

Logic Diagram

30042203

元器件交易网

DS91M040

Pin Descriptions

Number

1, 3, 5, 7

26, 28, 13, 15

Name

I/O, Type

O, LVCMOS

I, LVCMOS

Receiver output pin.

Receiver enable pin: When RE is high, the receiver is disabled.

When RE is low, the receiver is enabled. There is a 300 kΩ pullup

resistor on this pin.

Driver enable pin: When DE is low, the driver is disabled. When

DE is high, the driver is enabled. There is a 300 kΩ pulldown

resistor on this pin.

Driver input pin.

Ground pin and pad.

Non-inverting driver output pin/Non-inverting receiver input pin

Inverting driver output pin/Inverting receiver input pin

Power supply pin, +3.3V ± 0.3V

Failsafe enable pin with a 300 kΩ pullup resistor. This pin

enables Type 2 receiver on inputs 0 and 2.

FSEN1 = L --> Type 1 receiver inputs

FSEN1 = H --> Type 2 receiver inputs

Failsafe enable pin with a 300 kΩ pullup resistor. This pin

enables Type 2 receiver on inputs 1 and 3.

FSEN2 = L --> Type 1 receiver inputs

FSEN2 = H --> Type 2 receiver inputs

Master enable pin. When MDE is H, the device is powered up.

When MDE is L, the device overrides all other control and powers

down.

Description

25, 27, 14, 16DEI, LVCMOS

2, 4, 6, 8

31, DAP

17, 19, 21, 23

18, 20, 22, 24

11, 12, 29, 30

GND

FSEN1

I, LVCMOS

Power

I/O, M-LVDS

Power

I, LVCMOS

9FSEN2I, LVCMOS

10MDEI, LVCMOS

M-LVDS Receiver Types

The EIA/TIA-899 M-LVDS standard specifies two different

types of receiver input stages. A type 1 receiver has a con-

ventional threshold that is centered at the midpoint of the input

amplitude, V

/2. A type 2 receiver has a built in offset that is

100mV greater then V

/2. The type 2 receiver offset acts as

a failsafe circuit where open or short circuits at the input will

always result in the output stage being driven to a low logic

state.

30042240

FIGURE 1. M-LVDS Receiver Input Thresholds

元器件交易网

Absolute Maximum Ratings

(Note 4)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Power Supply Voltage−0.3V to +4V

LVCMOS Input Voltage−0.3V to (V

+ 0.3V)

LVCMOS Output Voltage−0.3V to (V

+ 0.3V)

M-LVDS I/O Voltage−5.5V to +5.5V

M-LVDS Output Short Circuit

Current DurationContinuous

Junction Temperature+140°C

Storage Temperature Range−65°C to +150°C

Lead Temperature Range

Soldering (4 sec.)+260°C

Maximum Package Power Dissipation @ +25°C

SQ Package833 mW

Derate SQ Package6.67 mW/°C above +25°C

Package Thermal Resistance

+150°C/W

+63.8°C/W

ESD Susceptibility

HBM (Note 1)

MM (Note 2)

CDM (Note 3)

Note 1:Human Body Model, applicable std. JESD22-A114C

Note 2:Machine Model, applicable std. JESD22-A115-A

Note 3:Field Induced Charge Device Model, applicable std.

JESD22-C101-C

≥

8 kV

≥

250V

≥

1250V

Recommended Operating

Conditions

Supply Voltage, V

Voltage at Any Bus Terminal

MinTypMaxUnits

3.03.33.6V

−1.4 +3.8V

(Separate or Common-Mode)

Differential Input Voltage V

2.4V

LVTTL Input Voltage High V

2.0 V

LVTTL Input Voltage Low V

0 0.8V

Operating Free Air

Temperature T

−40+25+85°C

DC Electrical Characteristics

Symbol

M-LVDS Driver

ΔV

OS(SS)

Differential output voltage magnitude

Parameter

(Notes 5, 6, 7, 9)

Over recommended operating supply and temperature ranges unless otherwise specified.

Conditions

= 50Ω, C

= 5 pF

Figures 2, 4

= 50Ω, C

= 5 pF

Figures 2, 3

Figure 5

= 50Ω, C

= 5pF, C

= 0.5 pF

Figures 7, 8

Min

480

−50

0.3

−0.2V

Typ

1.6

100

2.7

0.28

-50

Max

650

+50

2.1

+50

2.4

1.2V

150

0.4

-90

Units

μA

Change in differential output voltage magnitude

between logic states

Steady-state common-mode output voltage

|ΔV

OS(SS)

Change in steady-state common-mode output

voltage between logic states

A(OC)

B(OC)

P(H)

P(L)

IT+

IT−

OSR

Maximum steady-state open-circuit output voltage

Voltage overshoot, low-to-high level output

(Note 12)

Voltage overshoot, high-to-low level output

(Note 12)

High-level input current (LVTTL inputs)

Low-level input current (LVTTL inputs)

Input Clamp Voltage (LVTTL inputs)

Differential short-circuit output current (Note 8)

Positive-going differential input voltage threshold

Negative-going differential input voltage threshold

High-level output voltage (LVTTL output)

Low-level output voltage (LVTTL output)

TRI-STATE output current

= 2.0V

= 0.8V

= -18 mA

Figure 6

See Function Tables

= −8mA

= 8mA

= 0V or 3.6V

Type 1

Type 2

Type 1

Type 2

-15

-1.5

-43

−50

2.4

−10

M-LVDS Receiver

Short-circuit receiver output current (LVTTL output)V

= 0V

元器件交易网

DS91M040

Symbol

Parameter

Transceiver input/output current

Conditions

= 3.8V, V

= 1.2V

= 0V or 2.4V, V

= 1.2V

= −1.4V, V

= 1.2V

Transceiver input/output currentV

= 3.8V, V

= 1.2V

= 0V or 2.4V, V

= 1.2V

= −1.4V, V

= 1.2V

A(OFF)

Transceiver input/output differential current (I

− I

)

= V

, −1.4V

≤

3.8V

Transceiver input/output power-off currentV

= 3.8V, V

= 1.2V,

DE = V

= 1.5V

= 0V or 2.4V, V

= 1.2V,

DE = V

= 1.5V

= −1.4V, V

= 1.2V,

DE = V

= 1.5V

B(OFF)

Transceiver input/output power-off currentV

= 3.8V, V

= 1.2V,

DE = V

= 1.5V

= 0V or 2.4V, V

= 1.2V,

DE = V

= 1.5V

= −1.4V, V

= 1.2V,

DE = V

= 1.5V

AB(OFF)

A/B

Transceiver input/output power-off differential

current (I

A(OFF)

− I

B(OFF)

)

Transceiver input/output capacitance

Transceiver input/output differential capacitance

Transceiver input/output capacitance balance (C

)

Driver Supply Current

TRI-STATE Supply Current

Receiver Supply Current

Power Down Supply Current

= 50Ω, DE = H, RE = H

DE = L, RE = H

DE = L, RE = L

MDE = L

= V

, −1.4V

≤

3.8V,

= 1.5V, DE = 1.5V

= OPEN

Min

−20

−32

−20

−32

−4

−20

−32

−20

−32

−4

Typ

7.8

Max

+20

Units

µA

M-LVDS Bus (Input and Output) Pins

SUPPLY CURRENT (V

)

CCD

CCZ

CCR

CCPD

Note 4:“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions.

Note 5:The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 6:Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V

and

ΔV

Note 7:Typical values represent most likely parametric norms for V

= +3.3V and T

= +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 8:Output short circuit current (I

) is specified as magnitude only, minus sign indicates direction only.

Note 9:C

includes fixture capacitance and C

includes probe capacitance.

元器件交易网

Switching Characteristics

Symbol

DRIVER AC SPECIFICATIONS

PLH

PHL

SKD1

SKD2

SKD3

SKD4

TLH

THL

PZH

PZL

PLZ

PHZ

PLH

PHL

SKD1A

SKD1B

SKD2

SKD3

SKD4

TLH

THL

PZH

PZL

PLZ

PHZ

WKUP

MAX

Parameter

(Notes 10, 11, 17)

Over recommended operating supply and temperature ranges unless otherwise specified.

Conditions

= 50Ω, C

= 5 pF,

= 0.5 pF

Figures 7, 8

= 50Ω, C

= 5 pF,

= 0.5 pF

Figures 9, 10

= 15 pF

Figures 11, 12, 13

= 500Ω, C

= 15 pF

Figures 14, 15

Min

1.5

1.2

1.5

0.3

125

Typ

3.3

100

0.8

2.0

7.5

8.0

7.0

3.0

3.1

475

0.6

1.1

0.65

3.5

Max

5.5

125

200

1.6

3.0

11.5

4.5

325

800

300

1.2

1.6

5.5

500

Units

MHz

Differential Propagation Delay Low to High

Differential Propagation Delay High to Low

Pulse Skew (Notes 12, 13)

Channel-to-Channel Skew (Notes 12, 14)

Part-to-Part Skew (Notes 12, 15)

Part-to-Part Skew (Notes 12, 16)

Rise Time (Note 12)

Fall Time (Note 12)

Enable Time (Z to Active High)

Enable Time (Z to Active Low )

Disable Time (Active Low to Z)

Disable Time (Active High to Z)

Propagation Delay Low to High

Propagation Delay High to Low

Pulse Skew (Receiver Type 1)

(Notes 12, 13)

Pulse Skew (Receiver Type 2)

(Notes 12, 13)

Channel-to-Channel Skew (Notes 12, 14)

Part-to-Part Skew (Notes 12, 15)

Part-to-Part Skew (Notes 12, 16)

Rise Time (Note 12)

Fall Time (Note 12)

Enable Time (Z to Active High)

Enable Time (Z to Active Low)

Disable Time (Active Low to Z)

Disable Time (Active High to Z)

Wake Up Time (Note 12)

(Master Device Enable (MDE) time)

Maximum Operating Frequency (Note 12)

RECEIVER AC SPECIFICATIONS

GENERIC AC SPECIFICATIONS

Note 10:The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 11:Typical values represent most likely parametric norms for V

= +3.3V and T

= +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 12:Specification is guaranteed by characterization and is not tested in production.

Note 13:t

SKD1

, |t

PLHD

− t

PHLD

|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative

going edge of the same channel.

Note 14:t

SKD2

, Channel-to-Channel Skew, is the difference in propagation delay (t

PLHD

or t

PHLD

) among all output channels.

Note 15:t

SKD3

, Part-to-Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to

devices at the same V

and within 5°C of each other within the operating temperature range.

Note 16:t

SKD4

, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over

recommended operating temperature and voltage ranges, and across process distribution. t

SKD4

is defined as |Max − Min| differential propagation delay.

Note 17:C

includes fixture capacitance and C

includes probe capacitance.

Note 18:Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subracted geometrically.

元器件交易网

DS91M040

Test Circuits and Waveforms

30042214

FIGURE 2. Differential Driver Test Circuit

30042224

FIGURE 3. Differential Driver Waveforms

30042222

FIGURE 4. Differential Driver Full Load Test Circuit

30042212

FIGURE 5. Differential Driver DC Open Test Circuit

元器件交易网

30042225

FIGURE 6. Differential Driver Short-Circuit Test Circuit

30042216

FIGURE 7. Driver Propagation Delay and Transition Time Test Circuit

30042218

FIGURE 8. Driver Propagation Delays and Transition Time Waveforms

元器件交易网

DS91M040

30042219

FIGURE 9. Driver TRI-STATE Delay Test Circuit

30042221

FIGURE 10. Driver TRI-STATE Delay Waveforms

30042215

FIGURE 11. Receiver Propagation Delay and Transition Time Test Circuit

元器件交易网

30042217

FIGURE 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms

30042223

FIGURE 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms

30042213

FIGURE 14. Receiver TRI-STATE Delay Test Circuit

元器件交易网

DS91M040

30042220

FIGURE 15. Receiver TRI-STATE Delay Waveforms

元器件交易网

Truth Tables

DS91M040 Transmitting

Inputs

X — Don't care condition

Z — High impedance state

Outputs

DS91M040 as Type 1 Receiving

Inputs

FSEN

A − B

Output

FSEN

DS91M040 as Type 2 Receiving

Inputs

A − B

Output

≥

+0.05V

≤

−0.05V

≥

+0.15V

≤

+0.05V

X — Don't care condition

Z — High impedance state

X — Don't care condition

Z — High impedance state

DS91M040 Type 1 Receiver Input Threshold Test Voltages

Applied Voltages

2.400V

0.000V

3.800V

3.750V

−1.350V

−1.400V

0.000V

2.400V

3.750V

3.800V

−1.400V

−1.350V

Resulting Differential Input

Voltage

2.400V

−2.400V

0.050V

−0.050V

0.050V

−0.050V

Resulting Common-Mode

Input Voltage

ICM

1.200V

3.775V

−1.375V

Receiver

Output

H — High Level

L — Low Level

Output state assumes that the receiver is enabled (RE = L)

DS91M040 Type 2 Receiver Input Threshold Test Voltages

Applied Voltages

2.400V

0.000V

3.800V

−1.250V

−1.350V

0.000V

2.400V

3.650V

3.750V

−1.400V

Resulting Differential Input

Voltage

2.400V

−2.400V

0.150V

0.050V

0.150V

0.050V

Resulting Common-Mode

Input Voltage

1.200V

3.725V

3.775V

−1.325V

−1.375V

Receiver

Output

H — High Level

L — Low Level

Output state assumes that the receiver is enabled (RE = L)

元器件交易网

DS91M040

Typical Performance

Driver Rise Time as a Function of Temperature

30042250

Driver Propagation Delay (tPLHD) as a Function of

Temperature

30042252

Driver Fall Time as a Function of Temperature

30042251

Driver Propagation Delay (tPHLD) as a Function of

Temperature

30042253

Driver Output Signal Amplitude as a Function of

Resistive Load

30042258

元器件交易网

Driver Power Supply Current as a Function of Frequency

30042254

Receiver Propagation Delay (tPLHD) as a Function of

Input Common Mode Voltage

30042256

Receiver Power Supply Current as a Function of

Frequency

30042255

Receiver Propagation Delay (tPHLD) as a Function of

Input Common Mode Voltage

30042257

元器件交易网

DS91M040

Physical Dimensions

inches (millimeters) unless otherwise noted

Order Number DS91M040TSQ

See NS package Number SQA32A

(See AN-1187 for PCB Design and Assembly Recommendations)

元器件交易网

Notes

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

Products

Amplifiers

Audio

Clock Conditioners

Data Converters

Displays

Ethernet

Interface

LVDS

Power Management

Switching Regulators

LDOs

LED Lighting

PowerWise

Serial Digital Interface (SDI)

Temperature Sensors

Wireless (PLL/VCO)

/amplifiers

/audio

/timing

/adc

/displays

/ethernet

/interface

/lvds

/power

/switchers

/ldo

/led

/powerwise

/sdi

/tempsensors

/wireless

WEBENCH

Analog University

App Notes

Distributors

Green Compliance

Packaging

Design Support

/webench

/AU

/appnotes

/contacts

/quality/green

/packaging

/quality

/refdesigns

/feedback

Quality and Reliability

Reference Designs

Feedback

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