2024年7月13日发(作者：门桃雨)
元器件交易网
HD74HC76
Dual J-K Flip-Flops (with Preset and Clear)
REJ03D0551-0200
(Previous ADE-205-423)
Rev.2.00
Oct 06, 2005
Description
Each flip-flop has independent J, K, preset, clear, and clock inputs and Q and Q outputs. This device is edge sensitive
to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent
of the clock and accomplished by a low logic level on the corresponding input.
Features
•
•
•
•
•
•
High Speed Operation: t
pd
(Clock to Q) = 21 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: I
CC
(static) = 2 µA max (Ta = 25°C)
Ordering Information
Part Name Package Type
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74HC76P DILP-16 pin
HD74HC76FPEL SOP-16 pin (JEITA)
P —
EL (2,000 pcs/reel)
PRSP0016DH-B
FP
(FP-16DAV)
Note: Please consult the sales office for the above package availability.
Function Table
Preset Clear Clock J K Q Q
Inputs Outputs
L H X X X H L
H L X X X L H
L L X X X H
H H
H H
H H
H H
L L
*1
H
No change
*1
L H L H
H L H L
Toggle
No change
No change
No change
H H
H H L X X
H H H X X
H H
X X
H : High level
L : Low level
X : Irrelevant
Note: 1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and
Clear go High simultaneously.
Rev.2.00, Oct 06, 2005 page 1 of 6
元器件交易网
HD74HC76
Pin Arrangement
1CK1
1PR2
1CLR3
1J4
V
CC
5
2CK
6
2PR
7
2CLR
8
(Top view)
K
CK
J
CLR
Q
PR
Q
J
CK
K
PR
Q
CLR
Q
16
1K
15
1Q
14
1Q
13
GND
12
2K
11
2Q
10
2Q
9
2J
Logic Diagram (1/2)
PR
CLR
J
K
#
CK
CK
#
CK
#
CK
CK
CK
CK
#
CK
Q
Q
CK
CK
#
CK
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage range V
CC
–0.5 to 7.0 V
Input / Output voltage
Input / Output diode current
Output current
V
CC
, GND current
Power dissipation
Storage temperature
Vin, Vout
I
IK
, I
OK
I
O
I
CC
or I
GND
–0.5 to V
CC
+0.5 V
±20 mA
±25 mA
±50 mA
P
T
500 mW
Tstg –65 to +150 °C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.2.00, Oct 06, 2005 page 2 of 6
2024年7月13日发(作者：门桃雨)
元器件交易网
HD74HC76
Dual J-K Flip-Flops (with Preset and Clear)
REJ03D0551-0200
(Previous ADE-205-423)
Rev.2.00
Oct 06, 2005
Description
Each flip-flop has independent J, K, preset, clear, and clock inputs and Q and Q outputs. This device is edge sensitive
to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent
of the clock and accomplished by a low logic level on the corresponding input.
Features
•
•
•
•
•
•
High Speed Operation: t
pd
(Clock to Q) = 21 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: I
CC
(static) = 2 µA max (Ta = 25°C)
Ordering Information
Part Name Package Type
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74HC76P DILP-16 pin
HD74HC76FPEL SOP-16 pin (JEITA)
P —
EL (2,000 pcs/reel)
PRSP0016DH-B
FP
(FP-16DAV)
Note: Please consult the sales office for the above package availability.
Function Table
Preset Clear Clock J K Q Q
Inputs Outputs
L H X X X H L
H L X X X L H
L L X X X H
H H
H H
H H
H H
L L
*1
H
No change
*1
L H L H
H L H L
Toggle
No change
No change
No change
H H
H H L X X
H H H X X
H H
X X
H : High level
L : Low level
X : Irrelevant
Note: 1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and
Clear go High simultaneously.
Rev.2.00, Oct 06, 2005 page 1 of 6
元器件交易网
HD74HC76
Pin Arrangement
1CK1
1PR2
1CLR3
1J4
V
CC
5
2CK
6
2PR
7
2CLR
8
(Top view)
K
CK
J
CLR
Q
PR
Q
J
CK
K
PR
Q
CLR
Q
16
1K
15
1Q
14
1Q
13
GND
12
2K
11
2Q
10
2Q
9
2J
Logic Diagram (1/2)
PR
CLR
J
K
#
CK
CK
#
CK
#
CK
CK
CK
CK
#
CK
Q
Q
CK
CK
#
CK
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage range V
CC
–0.5 to 7.0 V
Input / Output voltage
Input / Output diode current
Output current
V
CC
, GND current
Power dissipation
Storage temperature
Vin, Vout
I
IK
, I
OK
I
O
I
CC
or I
GND
–0.5 to V
CC
+0.5 V
±20 mA
±25 mA
±50 mA
P
T
500 mW
Tstg –65 to +150 °C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.2.00, Oct 06, 2005 page 2 of 6