2024年4月6日发(作者：魏忆彤)
October 1997
FDC6320C
Dual N & P Channel , Digital FET
General Description Features
N-Ch 25 V, 0.22 A, R
DS(ON)
= 5
Ω
@ V
GS
= 2.7 V.
P-Ch 25 V, -0.12 A, R
DS(ON)
= 13
Ω
@ V
GS
= -2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace NPN & PNP digital transistors.
These dual N & P Channel logic level enhancement mode field
effec transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
The device is an improved design especially for low voltage
applications as a replacement for bipolar digital transistors in
load switching applications. Since bias resistors are not
required, this dual digital FET can replace several digital
transistors with difference bias resistors.
SOT-23
SuperSOT
TM
-6SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
4
3
5
6
2
1
Absolute Maximum Ratings
T
A
= 25
o
C unless other wise noted
Symbol
V
DSS
, V
CC
V
GSS
, V
IN
I
D
, I
O
P
D
T
J
,T
STG
ESD
Parameter
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage,
Drain/Output Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
Operating and Storage Tempature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
Thermal Resistance, Junction-to-Ambient
(Note 1a)
Thermal Resistance, Junction-to-Case
(Note 1)
0.7
-55 to 150
6
°C
kV
N-Channel
25
8
0.22
0.5
0.9
P-Channel
-25
-8
-0.12
-0.5
W
Units
V
V
A
THERMAL CHARACTERISTICS
R
θJA
R
θ
J
C
140
60
°C/W
°C/W
© 1997 Fairchild Semiconductor C
/
DMOS Electrical Characteristics
(
T
A
= 25
O
C unless otherwise noted )
SymbolParameterConditions
Type
N-Ch
P-Ch
o
MinTypMaxUnits
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, I
D
= -250 µA
I
D
= 250 µA, Referenced to 25 C
I
D
= -250 µA, Referenced to 25
o
C
I
DSS
I
DSS
I
GSS
V
DS
= 20 V, V
GS
= 0 V,
T
J
= 55°C
Zero Gate Voltage Drain Current
Gate - Body Leakage Current
V
DS
=-20 V, V
GS
= 0 V,
T
J
= 55°C
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
ON CHARACTERISTICS
(Note 2)
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
T
J
=125°C
V
GS
= 4.5 V, I
D
= 0.4 A
V
GS
= -2.7 V, I
D
= -0.05 A
T
J
=125°C
V
GS
= -4.5 V, I
D
= -0.2 A
I
D(ON)
g
FS
On-State Drain Current
Forward Transconductance
V
GS
= 2.7 V, V
DS
= 5 V
V
GS
= -2.7 V, V
DS
= -5 V
V
DS
= 5 V, I
D
= 0.4 A
V
DS
= -5 V, I
D
= -0.2 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
N-Channel
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
P-Channel
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
9.5
11
6
7
1.3
1.4
pF
pF
pF
N-Ch
P-Ch
N-Ch
P-Ch
0.2
-0.05
0.2
0.135
S
P-Ch
0.65
-0.65
-2.1
1.9
0.85
-1
3.8
6.3
3.1
10.6
15
7.9
1.5
-1.5
5
9
4
13
21
10
A
V
P-Ch
25
-25
25
-20
1
10
-1
-10
100
-100
nA
nA
mV /
o
C
µA
µA
mV /
o
C
V
∆
BV
DSS
/
∆
T
J
N-Ch
P-Ch
N-Ch
∆
V
GS(th)
/
∆
T
J
V
GS(th)
R
DS(ON)
Gate Threshold Voltage Temp. Coefficient
Gate Threshold Voltage
Static Drain-Source On-Resistance
I
D
= 250 µA, Referenced to 25
o
C
I
D
= -250 µA, Referenced to 25
o
C
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= V
GS
, I
D
= -250 µA
V
GS
= 2.7 V, I
D
= 0.2 A
Ω
C
/
2024年4月6日发(作者：魏忆彤)
October 1997
FDC6320C
Dual N & P Channel , Digital FET
General Description Features
N-Ch 25 V, 0.22 A, R
DS(ON)
= 5
Ω
@ V
GS
= 2.7 V.
P-Ch 25 V, -0.12 A, R
DS(ON)
= 13
Ω
@ V
GS
= -2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace NPN & PNP digital transistors.
These dual N & P Channel logic level enhancement mode field
effec transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
The device is an improved design especially for low voltage
applications as a replacement for bipolar digital transistors in
load switching applications. Since bias resistors are not
required, this dual digital FET can replace several digital
transistors with difference bias resistors.
SOT-23
SuperSOT
TM
-6SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
4
3
5
6
2
1
Absolute Maximum Ratings
T
A
= 25
o
C unless other wise noted
Symbol
V
DSS
, V
CC
V
GSS
, V
IN
I
D
, I
O
P
D
T
J
,T
STG
ESD
Parameter
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage,
Drain/Output Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
Operating and Storage Tempature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
Thermal Resistance, Junction-to-Ambient
(Note 1a)
Thermal Resistance, Junction-to-Case
(Note 1)
0.7
-55 to 150
6
°C
kV
N-Channel
25
8
0.22
0.5
0.9
P-Channel
-25
-8
-0.12
-0.5
W
Units
V
V
A
THERMAL CHARACTERISTICS
R
θJA
R
θ
J
C
140
60
°C/W
°C/W
© 1997 Fairchild Semiconductor C
/
DMOS Electrical Characteristics
(
T
A
= 25
O
C unless otherwise noted )
SymbolParameterConditions
Type
N-Ch
P-Ch
o
MinTypMaxUnits
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, I
D
= -250 µA
I
D
= 250 µA, Referenced to 25 C
I
D
= -250 µA, Referenced to 25
o
C
I
DSS
I
DSS
I
GSS
V
DS
= 20 V, V
GS
= 0 V,
T
J
= 55°C
Zero Gate Voltage Drain Current
Gate - Body Leakage Current
V
DS
=-20 V, V
GS
= 0 V,
T
J
= 55°C
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
ON CHARACTERISTICS
(Note 2)
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
T
J
=125°C
V
GS
= 4.5 V, I
D
= 0.4 A
V
GS
= -2.7 V, I
D
= -0.05 A
T
J
=125°C
V
GS
= -4.5 V, I
D
= -0.2 A
I
D(ON)
g
FS
On-State Drain Current
Forward Transconductance
V
GS
= 2.7 V, V
DS
= 5 V
V
GS
= -2.7 V, V
DS
= -5 V
V
DS
= 5 V, I
D
= 0.4 A
V
DS
= -5 V, I
D
= -0.2 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
N-Channel
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
P-Channel
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
9.5
11
6
7
1.3
1.4
pF
pF
pF
N-Ch
P-Ch
N-Ch
P-Ch
0.2
-0.05
0.2
0.135
S
P-Ch
0.65
-0.65
-2.1
1.9
0.85
-1
3.8
6.3
3.1
10.6
15
7.9
1.5
-1.5
5
9
4
13
21
10
A
V
P-Ch
25
-25
25
-20
1
10
-1
-10
100
-100
nA
nA
mV /
o
C
µA
µA
mV /
o
C
V
∆
BV
DSS
/
∆
T
J
N-Ch
P-Ch
N-Ch
∆
V
GS(th)
/
∆
T
J
V
GS(th)
R
DS(ON)
Gate Threshold Voltage Temp. Coefficient
Gate Threshold Voltage
Static Drain-Source On-Resistance
I
D
= 250 µA, Referenced to 25
o
C
I
D
= -250 µA, Referenced to 25
o
C
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= V
GS
, I
D
= -250 µA
V
GS
= 2.7 V, I
D
= 0.2 A
Ω
C
/