2024年4月13日发(作者：阳以南)
元器件交易网
74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
March 1995
Revised February 2005
74LCX14
Low Voltage Hex Inverter
with 5V Tolerant Schmitt Trigger Inputs
General Description
The LCX14 contains six inverter gates each with a Schmitt
trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free out-
put signals. In addition, they have a greater noise margin
than conventional inverters.
The LCX14 has hysteresis between the positive-going and
negative-going input thresholds (typically 1.0V) which is
determined internally by transistor ratios and is essentially
insensitive to temperature and supply voltage variations.
The inputs tolerate voltages up to 7V allowing the interface
of 5V, 3V and 2.5V systems.
The 74LCX14 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s5V tolerant inputs
s2.3V–3.6V V
CC
specifications provided
s6.5 ns t
PD
max (V
CC
3.3V), 10
P
A I
CC
max
sPower down high impedance inputs and outputs
s
r
24 mA output drive (V
CC
3.0V)
sImplements patented noise/EMI reduction circuitry
sLatch-up performance exceeds JEDEC 78 conditions
sESD performance:
Machine model
!
200V
Human model
!
2000V
sLeadless Pb-Free DQFN package
Ordering Code:
Order Number
74LCX14M
74LCX14MX_NL
(Note 2)
74LCX14SJ
74LCX14BQX
(Note 1)
74LCX14MTC
74LCX14MTCX_NL
(Note 2)
Package
Number
M14A
M14A
M14D
MLP014A
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: DQFN package available in Tape and Reel only.
Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor
元器件交易网
7
4
L
C
X
1
4
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Pad Assignments for DQFN
Description
Inputs
Outputs
Pin Descriptions
Pin Names
I
n
O
n
Truth Table
Input
A
L
H
Output
O
H
L
(Top View)
2
元器件交易网
74LCX14
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
ValueConditionsUnits
V
V
Output in HIGH or LOW State (Note 4)
V
I
2024年4月13日发(作者：阳以南)
元器件交易网
74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
March 1995
Revised February 2005
74LCX14
Low Voltage Hex Inverter
with 5V Tolerant Schmitt Trigger Inputs
General Description
The LCX14 contains six inverter gates each with a Schmitt
trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free out-
put signals. In addition, they have a greater noise margin
than conventional inverters.
The LCX14 has hysteresis between the positive-going and
negative-going input thresholds (typically 1.0V) which is
determined internally by transistor ratios and is essentially
insensitive to temperature and supply voltage variations.
The inputs tolerate voltages up to 7V allowing the interface
of 5V, 3V and 2.5V systems.
The 74LCX14 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s5V tolerant inputs
s2.3V–3.6V V
CC
specifications provided
s6.5 ns t
PD
max (V
CC
3.3V), 10
P
A I
CC
max
sPower down high impedance inputs and outputs
s
r
24 mA output drive (V
CC
3.0V)
sImplements patented noise/EMI reduction circuitry
sLatch-up performance exceeds JEDEC 78 conditions
sESD performance:
Machine model
!
200V
Human model
!
2000V
sLeadless Pb-Free DQFN package
Ordering Code:
Order Number
74LCX14M
74LCX14MX_NL
(Note 2)
74LCX14SJ
74LCX14BQX
(Note 1)
74LCX14MTC
74LCX14MTCX_NL
(Note 2)
Package
Number
M14A
M14A
M14D
MLP014A
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: DQFN package available in Tape and Reel only.
Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor
元器件交易网
7
4
L
C
X
1
4
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Pad Assignments for DQFN
Description
Inputs
Outputs
Pin Descriptions
Pin Names
I
n
O
n
Truth Table
Input
A
L
H
Output
O
H
L
(Top View)
2
元器件交易网
74LCX14
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
ValueConditionsUnits
V
V
Output in HIGH or LOW State (Note 4)
V
I